For a long time, analog-to-digital converters (ADCs) play a critical role in scientific, industrial, medical and consuming electronic products, especially in wireless communications, audio and video processing and commercial electronic applications.
Although the analog-to-digital converters have many different types, their structure is mainly configured as parallel or flash architectures, the conversion rate is also controlled with an external clock, wherein one action is executed within one clock cycle, furthermore, the number of their output pins is determined according to their output bit number. Such a structure and design of the analog-to-digital converter not only slow down the overall operation, consuming substantial chip size, but also consume unnecessary power.
According to the above drawbacks in the prior art, the applicant uses a pipeline design to reduce the chip size, the cost and the power consumption of the analog-to-digital converter, and double its conversion rate by triggering with both the rising and falling edge of the clock, and sharing the output pins in common. Thus the invention of the case “the pipeline analog-to-digital converter” would be the best way to solve the deficiencies of conventional means.